1. Field of the Invention
The present invention generally relates to nonvolatile semiconductor memories and more particularly, to a circuit configuration of data write and data erase in a nonvolatile semiconductor memory.
2. Description of the Prior Art
FIG. 10 shows a memory cell circuit of a conventional electrically erasable programmable read-only memory (EEPROM). The conventional memory cell circuit includes memory cells 221 to 223 and a peripheral circuit of the memory cells 221 to 223. The peripheral circuit includes a word line 224, a source line 225, a power line 226, bit lines 227 to 229, bit line drivers 230 to 232, data latch circuits 233 to 235, a word line driver 236 and a data line 237. In FIG. 10, each of the memory cells 221 to 223 is constituted by a metal-oxide-semiconductor (MOS) transistor in which a floating gate FG is formed on a channel connecting a source and a drain and a control gate CG for controlling potential of the channel is formed on the floating gate FG.
The word line 224 is connected to the control gates CG of the memory cells 221 to 223 and potential of the word line 224 is changed by the word line driver 236. The source line 225 is connected to the sources of the memory cells 221 to 223 and a distal end of the source line 225 is grounded. The bit lines 227 to 229 are, respectively, connected to the drains of the memory cells 221 to 223 such that the memory cells 221 to 223 exchange data with the peripheral circuit via the bit lines 227 to 229. By using a high voltage Vpp supplied through the power line 226, the bit line drivers 230 to 232 apply to the bit lines 227 to 229 outputs corresponding to data of the data latch circuits 233 to 235, respectively. The data line 237 is provided for exchanging data with an external device and connects the data latch circuits 233 to 235 to a data input/output port (not shown) for the external device.
In the conventional EEPROM of FIG. 10, when data is written is one of the memory cells 221 to 223, for example, the data cell 221, the data is initially latched from the data input/output port to all the data latch circuits 233 to 235 by way of the data line 237. Then, potential of the bit line 227 connected to the memory cell 221 for data write is raised by the bit line driver 230 and potential of the word line 224 is raised by the word line driver 236. In the meantime, since potential of the source line 225 is maintained at a ground level, a high voltage is applied between the source and the drain of the memory cell 221, so that hot electrons are generated at the channel by the high electric field. The hot electrons are attracted by the high potential of the floating gate FG of the memory cell 221 so as to be injected into the floating gate FG of the memory cell 221 and thus, a gate voltage threshold value at which electric current starts flowing between the source and the drain of the memory cell rises. When the gate voltage threshold value of the memory cell 221 has reached a desired value, the potential of the word line 224 and the potential of the bit line 227 connected to the memory cell 221 for data write are lowered and thus, data write is completed.
In the above described data write operation of the conventional EEPROM, since an initial period required for data latch is far shorter than a latter period required for raising the gate voltage threshold value of the memory cell to the desired value by generating the hot electrons, the data is simultaneously written in as many memory cells as possible by using such a circuit as shown in FIG. 10 such that write time per unit data quantity is reduced, thereby resulting in improvement of its operating efficiency.
However, in the above conventional EEPROM, as the number of the memory cells for simultaneous data write increases, electric current flowing through the memory cells increases immediately after start of data write and a current peak occurs. Therefore, current carrying capacity of the source line 225 and the power line 226 should be designed to be large in conformity with the current peak. Furthermore, in case the high voltage Vpp supplied to the bit lines 227 to 229 is generated internally, boosting capability of a booster should also be designed to be large in conformity with the current peak. As a result, such a problem arises that these design conditions run counter to recent industrial trends towards miniaturization and lower supply voltage.
Thus, in order to lower the current peak necessary for data write, Japanese Patent Laid-Open Publication No. 2001-15716 (2001) proposes a semiconductor memory unit in which a constant-current element 240 for restricting to a predetermined value a drain current supplied to the drains of the memory cells 221 to 223 is inserted between a power source of the high voltage Vpp and the power line 226 in the conventional EEPROM of FIG. 10 as shown in FIG. 11. However, the drain current supplied to the drains of the memory cells 221 to 223 varies due to scatter of characteristics of the memory cells 221 to 223, etc. Therefore, in this known semiconductor memory unit, such inconveniences are incurred that in case the predetermined value of the drain current restricted by the constant-current element 240 is not optimal, the current peak required for data write cannot be lowered and a generation efficiency of the hot electrons cannot be increased.
In addition, Japanese Patent Laid-Open Publication No. 11-126487 (1999) discloses a nonvolatile semiconductor memory in which a drain voltage supplied for data write to drains of memory cells is changed in accordance with a drain current supplied to the drains of the memory cells such that not only accurate control of a threshold voltage of the memory cells is performed at high speed but deterioration of the memory cells is prevented. However, in this prior art nonvolatile semiconductor memory, the drain voltage is changed in accordance with the drain current. On the other hand, in the nonvolatile semiconductor memory of the present invention, a control gate voltage supplied to control gates of memory cells is changed in accordance with the drain current. In this respect, the prior art nonvolatile semiconductor memory is different from the nonvolatile semiconductor memory of the present invention.
Accordingly, an essential object of the present invention is to provide, with a view to eliminating the above mentioned drawbacks of prior art, a nonvolatile semiconductor memory in which write time can be shortened by not only lowering a current peak required for data write but raising a generation efficiency of hot electrons.
In order to accomplish this object of the present invention, a nonvolatile semiconductor memory according to the present invention is provided with a plurality of memory elements each having a control gate and a floating gate such that data is stored by electron injection to the floating gate and electron emission from the floating gate. The nonvolatile semiconductor memory includes an electric current detecting circuit for detecting a drain current supplied to a drain of each of the memory elements. In accordance with the drain current detected by the electric current detecting circuit, a voltage control circuit controls a control gate voltage supplied to the control gate of each of the memory elements.